1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for fabricating a semiconductor device, characterized by a washing step thereof.
2. Related Background Art
Degrees of integration of LSI including DRAM and MPU are increasing year after year, and with the increase of integration the design rules are decreasing and wiring tends to be formed in a multilayered structure. With progress in the development of multilayer interconnection structure, the CMP (Chemical Mechanical Polishing) technology to flatten a layer insulation film was introduced in fabrication of 0.35-xcexcm logic LSI in order to ensure the focus margin of exposure system. The chemical mechanical polishing (CMP) is a polishing method for carrying out polishing by making use of the chemical etching action of a chemical component contained in an abrasive and the mechanical polishing action which the abrasive originally has. The CMP techniques used in fabrication processes of LSI include planarization CMP and recess CMP; the planarization CMP is a technique for flattening device steps by polishing an insulation film of BPSG, SiO2, or the like deposited on the steps of devices such as transistors, wires, and so on; the recess CMP is a technique for forming an isolated buried element, a trench capacitor, a contact plug, or damascene wiring by burying an insulation film of SiO2 or the like or a metal film of poly-Si, Al, Cu, W, or the like in a hole or a trench formed on a device and removing the film deposited on portions except for the hole or trench portion by polishing. Either of the techniques has the capability of realizing global flatness, when compared with the SOG planarization technology and etch back planarization technology used heretofore.
Under such circumstances, it is considered that the layer-insulation-film-flattening CMP technology and the conventional wiring forming technology are adaptable to fabrication of LSI of 0.25-xcexcm and larger rules, but for 0.18-xcexcm and smaller rules, the buried wiring structure by dual damascene using the metal CMP technology will become essential for formation of multilayered wiring, because of factors such as the limit of etching technology of wiring material and guarantee of electromigration resistance.
A buried wiring forming method by dual damascene using the metal CMP will be described below referring to FIG. 26 to FIG. 32.
In FIG. 26, reference numeral 1 designates a p-type semiconductor substrate, 2 n-type wells, 3 high-concentration p+-type source electrodes, 4 high-concentration p+-type drain electrodes, and 5 gate electrodes, and low-concentration pxe2x88x92-type electric field relaxing regions 3xe2x80x2, 4xe2x80x2 for increasing the withstand voltage of transistor are provided around the source electrodes 3 and drain electrodes 4. Numeral 6 denotes selective oxide regions for element isolation.
Then, as shown in FIG. 27, NSG (non-doped glass) 7 is deposited by CVD or TEOS and thereafter this NSG 7 is polished and flattened by CMP. The CMP employed herein is polishing using an abrasive cloth, which is a lamination of a foam cloth such as IC-1000 generally used for CMP of layer insulation film and a cloth of nonwoven fabric type, and a silica-based slurry such as SC-1 using fumed silica. Then p-SiN (silicon nitride film formed by the plasma enhanced CVD process) 8 is deposited and thereafter p-SiO (silicon oxide film formed by the plasma enhanced CVD process) 9 is deposited.
Next, as shown in FIG. 28, wiring pattern 10 is formed in the p-SiO 9 by resist patterning and dry etching. On the occasion of the dry etching the p-SiN 8 is used as an etching stopper, whereby the wiring pattern 10 can be formed on a stable basis. Then contact pattern 11 is formed by resist patterning and dry etching.
Subsequently, as shown in FIG. 29, wiring material 12 is deposited. A method for depositing the wiring material 12 herein may be selected from a variety of methods, among which a sputter reflow method of Al- or Cu-based metal material is effective in terms of production cost, reliability, and enhancement of characteristics of device. An effective way to enhance the reliability and reflow characteristics is to form a layer of barrier metal such as Ti/TiN as a ground layer, prior to the above deposition by sputter reflow.
Next, as shown in FIG. 30, the CMP for metal is carried out to polish and flatten the wiring material 12, thereby forming buried wiring 13. The above described the method for forming the buried wiring by dual damascene. By the like method wiring 13xe2x80x2 of the second layer and wiring 13xe2x80x3 of the third layer can be formed as shown in FIG. 31 and FIG. 32, thereby obtaining the further multilayered structure of wiring.
As described above, the polishing by CMP is effective as means for planarization, but also has some points to be improved. One of them is the problem of washing after the CMP. Since the CMP step itself is a polishing step for machining the wafer surface with the abrasive in the form of a slurry, abrasive particles of the slurry and chips and products produced in the polishing step are adhering to the wafer surface after the CMP. These must be removed by washing. Since the wiring material is the Al- or Cu-based metal material, chemical washing with an acid or an alkali would pose the problem of corrosion thereof and is thus hardly applicable. Sufficient cleanliness is not achieved by only washing with pure water. As for scrubbing washing, which is physical washing using pure water, and a PVA sponge or a mohair brush, because the wiring material is the soft metal material, dust particles adhering to the wafer surface would be the cause of production of fine flaws called scratches on the surface of wiring material, which would pose the problem in reliability, such as electromigration.
In addition to the above methods, a washing method, for example, using field-ionized water with a low metal etching property has also keen proposed (H. Aoki, et al., 1994 VLSI Technical Dig., p 79 (1994)), but as presently employed the abrasive particles adhering to the wafer surface cannot be sufficiently removed by this method.
An object of the present invention is to provide a fabrication method of semiconductor device comprising, after formation of an electroconductive material film, a step capable of stably washing a surface of the electroconductive material film at high cleanliness without corrosion thereof and without production of scratch.
Another object of the present invention is to provide a fabrication method of semiconductor device comprising a step of forming an electroconductive material film on a substrate, a step of polishing the electroconductive material film, and a step of washing a polished surface of said electroconductive material film, wherein said washing step is a step of carrying out ultrasonic washing with a washing solution to which an ultrasonic wave is applied, prior to physical washing.
According to the present invention, the polished surface of the electroconductive material film is washed using the washing solution to which the ultrasonic wave is applied, prior to the physical washing, whereby chips made by polishing and abrasive particles of slurry can be effectively removed. By this method, the electroconductive material film for forming the wiring, electrodes, etc, can be washed without production of scratch, or with very little production thereof, and with high cleanliness. The fabrication method of semiconductor device according to the present invention as described can provide a semiconductor device having the electroconductive material member with the extremely flat surface, without a scratch, and with excellent reliability.